IEEE IEDM 2025 | 17-4 | Transistor-to-Package Thermal ...
Dec 6, 2010 · Physics-based thermal SPICE of NSs and CFET integrated with FEM enables a comprehensive thermal simulation from transistor level to package level. Self-heating in …
23-2 | First Demonstration of Three-Dimensional Thermal ...
Dec 6, 2010 · Thermal models were developed to predict the temperature distribution in double-side integrated transistors with a novel cooling strategy. This work establishes quantitative …
17-3 | Breaking Thermal Bottleneck in 3D HBM-on-GPU ...
Dec 6, 2010 · Stacking High Bandwidth Memory directly atop GPUs offers greater bandwidth and package density but introduces thermal challenges. This work presents a comprehensive …
17-5 | Thermal Evaluation and Comparison of CAA and GAA ...
Dec 6, 2010 · We carry out the first thermal simulations and comparison of channel-all-around (CAA) and gate-all-around (GAA) indium tin oxide (ITO) vertical channel transistors (VCTs), …
19-1 | First Comparative Thermal Evaluation of 2D ...
Dec 6, 2010 · Building on our thermal measurements of monolayer MoS2 and ultrathin HfO2, we use simulations to compare the thermal behavior of 2D- vs. Si-NS transistors at 6–12 nm gate …
IEEE IEDM 2025 | 17 | MS | Thermal Analyses for Novel ...
Dec 6, 2010 · The next two papers highlight thermal challenges and excellent modeling techniques in advanced packaging schemes in both 2D and 3D systems. The next paper …
38-8 | Thermal Mitigation Strategy for 3D Stacked Devices ...
Dec 6, 2010 · Rapid advancements in semiconductors—such as line miniaturization, 3D architectures, and chip stacking—are pushing thermal management challenges to new limits, …